As integrated circuits continue to scale to still smaller feature sizes, shrinking device geometry and differing material properties pose challenges for feature processing at 90 nm and below. One problem is that of etch undercut that occurs when etching a film stack consisting of several different materials. FIG. 22A illustrates a stack of materials to be etched using a photoresist 400. In this example, the stack consists of a metal layer 402, such as titanium, an insulating layer 404, such as tetraethylorthosilicate (TEOS) or other oxide, and other film layers, such as a polysilicon layer 406. The photoresist layer 400 is patterned on top, and all of the layers below are etched. Etch selectivity, which describes the etching rate of one material relative to the etching rate of another material, is poor between the Ti metal layer and the TEOS insulating layer. Accordingly, while polysilicon layer 406 is being cleaned, the TEOS insulating layer 404 is unintentionally etched as well, as illustrated in FIG. 22B. That is, as the polysilicon in polysilicon layer 406 underneath the TEOS insulating layer 404 is being etched vertically, the TEOS insulating layer 404 is etched laterally. Additional undercutting may further result from a subsequent cleaning prior to a deposition as depicted by FIG. 22C, resulting in an undercut trench 408. Such an undercut trench becomes difficult to reliably fill using conventional techniques without creating voids in the fill. These voids can be fatal to device performance.